1. Field of the Invention
The present invention generally relates to integrated circuit devices and, more particularly to comparator circuits utilized in integrated circuit devices.
2. Description of the Related Art
Integrated circuit devices (ICs) utilize comparator circuits for a variety of purposes. As an example, an IC device, such as a dynamic random access memory (DRAM) device may utilize a comparator circuit to determine the state of an input signal (e.g., an internal control signal) by comparing the voltage level of the input voltage signal against a reference voltage signal. Such a comparator circuit is commonly implemented utilizing a differential amplifier that generates an output signal by amplifying the difference between the input signal and the reference voltage signal.
FIG. 1A illustrates one example of a conventional comparator circuit 100A utilizing a differential amplifier circuit to generate an output signal VOUT indicative of the condition of an input signal VIN relative to a reference voltage VREF. The differential amplifier includes an arrangement of PMOS load transistors (MPA and MPB) and NMOS input transistors (MNA and MNB). The differential amplifier generates the single ended output VOUT that represents an amplification of the difference between VREF and VIN.
In operation, if the voltage level of VREF is greater than the voltage level of VIN, the current flowing through MNA (IA) will be greater than the current flowing through MNB (IB) and, thus, the potential at output node B will be high. On the other hand, if the voltage level of VREF is less than VIN, the current flowing through MNA (IA) will be less than the current flowing through MNB (IB) and, thus, the potential at output node B will be low. Unfortunately, in this arrangement, the differential amplifier suffers from constant current consumption (IREF), regardless of the state of the input signal VIN.
FIG. 1B illustrates an example of another type of conventional comparator circuit 100B utilizing a differential amplifier circuit with PMOS input transistors (MPA and MPB). In this arrangement, if the voltage level of VREF is less than the voltage level of VIN, the current flowing through MPA (IA) will be greater than the current flowing through MNB (IB) and, thus, the potential at output node B will be high. If the voltage level of VREF is greater than VIN, the current flowing through MPA (IA) will be less than the current flowing through MPB (IB) and, thus, the potential at output node B will be low. Unfortunately, the differential amplifier in this arrangement also suffers from constant current consumption (IREF), from comparator circuit 110B regardless of the state of the input signal VIN.
This constant current consumption makes utilizing these types of comparators problematic in applications requiring minimal power consumption, such as in DRAM devices used in portable electronics, such as laptop computers, mobile phones, and personal digital assistants (PDAs). Accordingly, there is a need for a comparator circuit with reduced current consumption.